Shift circuits including threshold or other logic gates and employing multiple-phase shift pulses



R. O. WINDER Oct. 6, 1970 SHIFT CIRCUITS INCLUDING THRESHOLD OR OTHER LOGIC GATES AND EMPLOYING MULTIPLE-PHASE SHIFT PULSES 3 Sheets-Sheet 1 Filed May 8. 1968 INVENTOR Foamr d W/wzfi 3,532,991 0 GATES s Sheets-Sheet z AND EMPLOYING SHIFT CIRCUITS INCLU Oct. 6, 1970 Filed may 8, 1968 INVENTOR Faazxr '0. W/

nrronur 3,532,991 0 GATES R. O. WINDER Oct. 6, 1970 SHIFT CIRCUITS INCLUDING THRESHOLD OR OTHER LOGI MULTIPLE-PHASE SHIFT PULSES AND EMPLOYING 3 Sheets-Sheet 5 Filed May 8, 1968 rel? 007F075 a nl4 Z VZ 3 N I 4 0 !f 1 7 w U 3/ 2 7 Z 10'' 4 H v m r H M W Van 4 United States Patent O 3,532,991 SHIFT CIRCUITS INCLUDING THRESHOLD OR OTHER LOGIC GATES AND EMPLOYING MUL- TIPLE-PHASE SHIFT PULSES Robert O. Winder, Princeton, N..I., assignor to RCA Corporation, a corporation of Delaware Filed May 8, 1968, Ser. No. 727,557 Int. Cl. H03k 23/00 US. Cl. 32837 18 Claims ABSTRACT OF THE DISCLOSURE Shift circuits such as ring counters employing threshold or other logic gates which produce, at adjacent stages, pulses in time sequence which slightly overlap and which produce, at alternate stages, pulses in time sequence which do not overlap. Multiple-phases are employed for shifting the stored information.

SUMMARY OF THE INVENTION The circuits of the invention include 11 stages. Two timing signals of different phase are applied to said stages. There is also applied to at least each stage after the first and second stages signals indicative of the state of that stage and signals indicative of the states of the two preceding stages.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of one form of ring counter according to the invention;

FIG. 2 is a drawing of waveforms present in the circuit of FIG. 1;

FIG. 3 is a block diagram of another form of ring counter according to the invention;

FIG. 4 is a drawing of waveforms present in the circuit of FIG. 3;

FIG. 5 is a block diagram of another form of ring counter according to the invention;

FIG. 6 is a sketch of a threshold gate which is the equivalent of the gates employed in the circuit of FIG. 3; and

FIG. 7 is a block diagram of another form of shift circuit according to the invention.

DETAILED DESCRIPTION The gates of FIG. 1 receive electrical signals which represent binary digits (bits) as inputs, and produce electrical signals which represent bits as outputs. To simplify the discussion which follows, the bits themselves are sometimes referred to rather than the signals which represent the bits.

The threshold gates shown in FIG. 1 are, in themselves, known. Each gate has a threshold T of four, has a total of seven input weights, and produces a normal and a complemented output. For example, the gate 10 produces a normal output w and a complemented output E. The numbers across the top of each block of FIG. 1 represent the weights accorded the respective inputs. Thus, for example in gate 10 the signal 5 which is applied to a weight 2 terminal has twice the effect on the operation of the gate as the signal 5, or the signal a. The term threshold of four implies that if four or more of the input weights represent the bit 1, the normal output of the gate represents a 1 and the complemented output represents a 0; if less than four of the input weights represent the bit 1, the normal output of the gate represents a O and the complemented output represents a l.

Circuits for gates of the general type shown in FIG. 1, are described in copending application, Threshold Gates and Circuit, Ser. No. 567,344 filed July 13, 1966, now Pat.

No. 3,487,316, by the present applicant and assigned to the same assignee as the present application.

The storage circuits of the present invention may be operated in open-loop fashion as shift registers or counters or may have feedback from the later to the earlier stages and operate as ring counters. In the former applications, the circuits may have any number, odd or even, of stages. When operated as ring counters, they must have an even number n of stages. For purposes of the present application, the various embodiments are illustrated as ring counters. The example chosen for illustration in FIG. 1 has four stages, 10-13 and the information present in the stages is shifted by overlapping, multiple-phase shift pulses a and b.

In the circuit of FIG. 1, the normal output of each gate is applied back to the same gate with weight 2. The complementary output of each gate is applied to the next adjacent gate forward with weight 2 and is applied also to the gate two stages forward with weight 1. The shift pulses a and b are both applied to each stage with weight 1.

In more mathematical terms, the circuit of FIG. 1 can be described as follows:

(1) The normal output x,- of the j gate is applied to the j gate with weight 2.

(2) The complementary output 0?,- of the gate is applied to the j 69 1th gate with weight 2, and to the j 69 2nd gate with weight 1.

(3) A shift wave of one phase is applied with weight 1 to all gates.

(4) A shift wave of a different phase which represents binary 1 during a period which overlaps the period the first shift wave represents binary 1 is applied to all gates with weight 1.

The symbols above have the following meanings:

represents modulo n addition; j refers to each gate of the counter.

The operation of the circuit of FIG. 1 is succinctly given in Table I below. In this table, the symbol S refers to the sum of the weights of the inputs of value 1 which are applied to the gate producing the output w and so on. The asterisks are employed to indicate a change in the value of an output of a gate.

TABLE I a b w SW :1: SK 1 Sy z S 0 1 1 4 0 1 0 3 l 6 l 1 1 4 0 2 1* 6 1 5 1 0 0* 1 0 3 1 6 1 4 0 0 0 2 0 3 l 5 0* 1 0 1 0 3 1* 6 1 4 0 1 1 1 1* 6 1 5 1 4 0 2 1 O 1 6 1 4 0* 1 0 3 0 0 1 5 0* l 0 1 0 3 0 1 1 4 0 1 0 3 1* 6 The discussion which follows shows by a number of examples, how the values above are arrived at. Assume first that the circuit is in the first state shown, that is wxyz=1001. Assume also that b=1 and a=0. Of the signals applied to gate 12, those having the value 1, are 55 and b, so that the total number of input weights of value 1 is 3. Assume now that the shift wave a changes its value from 0 to 1. This causes one additional input weight to gate 12 to become 1, so that the threshold T=4 of the gate is reached. The output of the gate therefore changes from to 1, and since this output provides an input of weight 2, six of the input weights then represent a 1. At the same time, four of the input weights to gate represent a 1. These are w=l, [1:1 and b=1.

Assume now that the shift wave [2 changes its value from 1 to 0. This causes only three of the input weights to gate 10 to have a value 1, so that the output w of this gate changes from 1 to 0. The result is that only one of the input weights ((1:1) to gate 10 now has the value 1.

Analysis similar to the above can be made for each state of the counter of FIG. 1. These various states are illustrated in FIG. 2, where the relatively positive portion of each wave arbitrarily is chosen to represent the bit 1 and the relatively negative portion of each wave is chosen to represent the bit 0. For one particular application, the complementary signals produced by gates 10 and 12 and the normal signals produced by gates 11 and 13 may be employed as the output signals of the counter. With this choice, the singals of value 1 produced by adjacent stages of the counter slightly overlap and are in time sequence and the signals of value 1 produced by alternate stages of the counter do not overlap and are in time sequence.

Another form of the invention is shown in FIG. 3. It has an even number n of stages just as the circuit of FIG. 1 and, for purposes of the present application, 12 is chosen to be four (stages 21-24). The gates each have a total of five input weights and a threshold of two. The normal output of each gate is applied back to the same gate with weight 1 and is applied to the next adjacent gate forward, also with weight 1. The complementary output of each gate is applied to the gate two stages forward with weight 1. A shift wave a of one phase is applied to alternate stages 21 and 23 with Weight 2, and a shift wave b of another phase is applied to alternate stages- 22 and 24, also with weight 2. The time during which the wave a represents the binary value 1 is not concurrent with the time during which the wave [2 represents the value 1, as is illustrated in FIG. 4. In this figure, as in the FIG. 2, it is assumed arbitrarily that the positivegoing portions of the respective waves represent the bit 1 and the negative-going portions the bit 0.

In more mathematical terms, the circuit of FIG. 3 can be described as follows:

1) The normal output x,- of the j gate is applied to the j gate with the weight 1, and the je nl gate with weight 1. The complementary output 5, of the j gate is applied to the gate with weight 1.

(2) The shift wave a is applied to alternate gates with weight 2.

(3) The shift wave b is applied to the remaining gates with weight 2.

The operation of the counter of FIG. 3 is succinctly given in Table II below.

TABLE II a b w S w a: S x y Sy 2 St 0 0 1 3 0 1 O O 1 2 0 1 1 3 1* 4 0 1 1 3 0 0 1 2 1 3 0 1 0* 0 1 0 1 3 1 3 1* 4 0 1 0 0 0* 0 1 2 1 3 0 1 0 1 0 1 1 3 1 3 1* 4 0 O 0 1 0* 0 1 2 1 3 1 0 1* 4 0 1 1 3 1 3 0 0 1 3 0 1 0* 0 1 2 The discussion which follows shows by a few examples how the values above are arrived at. Assume first that the circuit is in the first state shown, that is til wxyz=1 00 1, and a=0 and 11:0. Assume now that shift wave b changes its value to 1. Formerly, only one of the input weights to gate 22 had the value 1. Now three of the input weights have the value 1 and since the threshold of two of gate 22 is exceeded, x changes its value to 1. Now four of the input weights to gate 22 have the value 1.

Assume now that b changes its value to 0 and a remains 0. Formerly three of the input weights to gate 24 represented the bit 1. The change in b from 1 to 0 reduces the number of input weights of value 1 applied to gate 24 to 1 and this causes z to change from 1 to 0. The result is that all of the input weights to gate 24 represent a 0.

Analyses similar to the above may be made for each state of the counter of FIG. 3. The operation .of the counter is also illustrated in FIG. 4 where the complemented signals 5? Ir? 5 E are chosen as outputs.

While the gates of FIG. 3 are illustrated as having input weights 2, 1, 1, 1, and having a threshold of two, it may be desirable, in some circumstances, to employ instead the equivalent gate shown in FIG. 6. This gate is a 2, 2, 1, 1, 1 gate which has a threshold of four and a constant bias representing the bit 1 applied to a weight 2 input terminal of the gate. So that the reader may more easily see the analog the equivalent of gate 21 is illustrated in FIG. 6.

An important feature of the circuit of FIG. 3 and of the circuit of FIG. 5 described below is the ease with which they may be reset. If a and b are both made equal to 1, then E, Z5, 5 and 5 all become equal to 0 in both circuits. Then, with a=b=0, any desired stage can be set to 1 by changing to 0 an input of present value 1.

A third form of the present invention is illustrated in FIG. 5. This one has any even number of stages. For purposes of illustration, a counter with four such stages is shown. Each stage comprises two NOR gates such a 31 and 32. The output of each upper NOR gates serves as one input to the lower NOR gate. The output of each lower NOR gate is applied to the upper NOR gate of the same stage and the upper NOR gate of the next adjacent stage. The output of each lower NOR gate is also applied to the lower NOR gate of the stage two stages ahead. A shift wave a of one phase is applied to the lower NOR gates of alternate stages and a shift wave 1) of other phase is applied to the lower NOR gates of the remaining stages. These waves a and b are shown in FIG. 4.

In mathematical terms the circuit of FIG. 5 can be described in the following way. In this description, uj refers to the upper NOR gate of the j stage and lj refers to the lower NOR gate of the F stage.

(1) The output 5 of the NOR gate lj of each j stage is applied to the NOR gate uj of the stage and the NOR gate uj E9 1 of the stage. It is also applied to the NOR gate Zj Q9 2 n of the j G} 2nd stage.

(2) The output of the NOR gate uj of the j stage is applied to the NOR gate lj of the j stage.

(3) The shift wave a is applied to the lower NOR gates of alternate stages.

(4) The shift wave b is applied to the lower NOR gate of the remaining stages.

The waves a and b do not have the value 1 concurrently.

The operation of the circuit of FIG. 5 is succinctly given in Table III below. The waveforms are identical to those of FIG. 4.

TABLE III In the operation of the circuit of FIG. 5, while each stage is not logically identical to the corresponding stage of the FIG. 3 circuit, they are the equivalent in these portions of their truth tables they are called upon to implement. Therefore, for purposes of the present application, they may be considered to be logically equivalent.

The equation which describes the operation of each stage j of the circuit of FIG. 3 is:

jl i -1, 14] where:

x, is the input the f stage receives from the j stage and an output of the j x,- is the input the stage receives from the stage, where represents modulo n subtraction, 5,; is the input of the W stage receives from the stage, and a is assumed to be the shift pulse applied to the j stage (the result is similar for b substituted for a).

it is this portion of .the truth table which is involved in the operation of the circuits of FIGS. 3 and 5.

TABLE IV ooooooo-u-u oc HHHOOOOQHHH HOOO HHl-HI- t3 HHOQCHHHHHQ- In the table above x represents the new value of the output of the j stage, 5, represents the input applied to the j stage by the j 9 2nd stage. x,- represents the input applied to the j stage by the j 9 1th stage. p represents the present effective value of the signal fed back from the output of the stage to its input. Note that in FIG. 3, the normal output x is fed back whereas in FIG. 5, the output 5, is fed back. However, in FIG. 5, the upper gate of the j stage effectively inverts the fed back signal. For example, if 5,:1 the output x,,,- of the upper gate ui of the stage is 0. And, in those portions of the truth table of interest in the operation of the counter, if 5 :0, then x,,,-=1. Accordingly, the table is valid for both circuits.

The table above is more detailed then previous tables in that it includes some unstable circuit conditions. Thus, rows 2, 5, 7 and 10 represent transitory conditions of the circuit. Row 11 of the table is the same as row 1.

In the introductory portion of this application, it is mentioned that the circuits of the present invention can be operated in open-loop fashion as well as in closed-loop, ring counter fashion. To illustrate how this may be accomplished, a modified form of the circuit of FIG. 3 is shown in FIG. 7. The first stage 41 of the circuit is a 3- input majority gate which receives a start pulse 11, a shift pulse b and a feedback pulse x. The second stage 42 is a threshold gate having a threshold of 3 and input weights 2, 1, 1, 1. The third, fourth and following stages of the counter are 2, 2, 1, 1, 1 gates with a threshold of 4. It is to be understood that there may be any number, odd or even, of such 2, 2, 1, 1, 1 gates and that only two of these gates are shown for purposes of the present application.

The counter of FIG. 7 operates in the following manner. First a and b are both made equal to 1 and h is made equal to 1. This causes all of the outputs Z13, lj, 5 and so on to be 0. Next a and b are both made equal to 0 and the start pulse h is also made equal to 0. This causes E5 to have the value 1. The x=0 applied to gate 42 causes its output to change to 3 :0. z, aa, and so on remain equal to 1.

The start signal h is now made equal to 1 again. x remains of the same value, that is, x=0 (since b and x are 0). Now the shift pulses a and b start as in FIG. 4. However, the first shift pulse to assume the value 1 is the b pulse. When b changes to 1 during the time h is 1, x changes to 1. y remains 0 and a and y=. Z and aa remain equal to 1. Now, when b changes back to 0 (a is also 0) four of the 7-input weights to gate 43 are 0 (y=0, 5:0, b =0) so that z becomes 0. Thereafter, the operation is exactly the same as the operation of the FIG. 3 circuit.

While not shown, it should be appreciated that the other circuits of the present application can be modified in the same general way as indicated in FIG. 7 to permit the circuits to operate in open-loop fashion.

While the invention has been illustrated in terms of ring counters with only four stages, it is to be understood that it is equally applicable to ring counters with greater even numbers of stages. Further, any output, complemented or normal, of any stage may serve as a counter output signal, the choice, in each case, depending upon engineering requirements. Finally, while a binary 1 is shown to correspond to a relatively positive signal the opposite convention may be chosen instead, that is, a 1 may be represented by a relatively negative signal and a 0 by a relatively positive signal.

What is claimed is:

1. A logic gate ring counter comprising, in combination:

an even number n of logic gate means;

means for applying an output of each j gate means back to the same gate means, where j refers to each of the gate means;

means for applying an output of each f gate means to the j 69 1th gate means, where represents modulo n addition;

means for applying an output of each j gate means to the j 69 2nd gate means, where GB n represents modulo n addition; and

means for applying multiple-phase shift pulses to said gate means.

2. A logic gate ring counter as set forth in claim 1 wherein each gate means comprises a threshold gate of input weights 2, 2, 1, 1 and a threshold of four, and having a normal and a complemented output.

3. A logic gate ring counter as set forth in claim 2 wherein the normal output x of each j threshold gate is applied to the same gate with weight 2 and the complemented output E of each j gate is applied to the j G; 1th

gate with weight 2 and to the j a 2nd gate with weight 1.

4. A logic gate ring counter as set forth in claim 3 wherein a shift pulse of one phase is applied to each threshold gate with weight 1 and a shift pulse of different phase is applied to each gate with weight 1, each shift pulse representing a binary 1 during a period which overlaps the period during which the other shift pulse represents a binary 1.

5. A logic gate ring counter as set forth in claim 1 wherein the normal output x of each gate is applied to the same gate with weight 1 and is applied to the gate with weight 1 and wherein the complemented output 5 of each gate is applied to the gate with weight 1, and further including means for applying a bias representing binary 1 with weight 2 to all gates.

6. A logic gate n'ng counter as set forth in claim 1 wherein a shift pulse of one phase is applied to alternate gates with Weight 2 and a shift pulse of other phase is applied to the remaining gates with weight 2, said two shift pulses representing binary 1 during mutually exclusive periods.

7. A logic gate ring counter as set forth in claim 1 wherein each gate means comprises a pair of NOR gates.

8. A logic gate ring counter as set forth in claim 7 wherein the output of the first NOR gate of the j pair of such gates is applied to the second NOR gate of the j pair of such gates, and the output of the second NOR gate of the f pair of such gates is applied to the first NOR gate of both the j and the pair of such gates, and also to the second NOR gate of the j 6 2nd pair of such gates.

9. A logic gate ring counter as set forth in claim 8 wherein a shift pulse of one phase is applied to alternate second NOR gates and a shift pulse of other phase is applied to the remaining second NOR gates, said two shift pulses representing binary 1 during mutually exclusive periods.

10. A threshold gate ring counter comprising, in combination:

an even number n of such threshold gates, each having a normal output and a complemented output; means for applying the normal output of each gate to an input to the same gate;

means for applying the complemented output of each j gate to at least the gate and with weight 1 to the gate, where refers to each gate and refers to modulo n addition; and

means for applying multiple-phase shift pulses to said gates.

11. A threshold gate ring counter as set forth in claim 10 wherein each threshold gate has input weights 2, 2, 1, 1, 1 and a threshold of four.

12. A threshold gate ring counter as set forth in claim 10 wherein each threshold gate has input weights 2, 1, 1, 1 and a threshold of 2.

13. A threshold gate ring counter as set forth in claim 11 wherein the normal output x of the F gate is applied with weight 2 to the j gate, the complemented output '5,- of the j gate is applied with weight 2 to the gate and with weight 1 to the j 2nd gate, and wherein the multiple-phase shift pulses comprise a pulse train of one phase and a pulse train of a second phase and wherein both trains of pulses are applied to each gate.

14. A threshold gate ring counter as set forth in claim 12 wherein the normal output x of the 1" gate is applied both to the fi and the gate, both with weight 1, the complemented output of each j gate is applied to the gate with weight 1, and wherein there are two trains of shift pulses, each of different phase, one train of pulses being applied, with weight 2, to alternate gates and the other train of pulses being applied, with weight 2, to the remaining gates.

15. In a logic gate shift circuit, n interconnected stages, where n is an integer greater than two, the operation of 9 10 each 1 one of said stages being defined by the following means for applying an output of each f gate means truth table: to the j+2 gate means, when a j+2 gate means is present; and

a 1-2 zs-i p s means for applying multiple-phase shift pulses to said 1 1 1 1 5 gate means. 8 1 i 17. A shift circuit comprising: 0 1 0 1 1 n stages, where n is an integer greater than two; i g 1 1 means for applying to said stages two timing signals 0 0 0 1 0 of different phase; and g 3 g g 10 means for applying to at least each stage after the first 1 0 1 0 1 and second stages, signals indicative of the state of 1 l 0 1 1 1 that stage and signals indicative of the states of the two preceding stages. where: 18. A circuit as set forth in claim 16 wherein each such a is a shift signal applied to the 1' stage; stage after the first and second stages is a 2, 2, 1, 1, 1 gate x,- is the new value of the output of the i stage; with a threshold of four. 5 is the input applied to the i stage by the '62 stage; x is the input applied to the j stage by the j91 References Cited and I f h 1 d h UNITED STATES PATENTS P if f ggfylg gfi sg g 0 t e app e 3,234,401 2/1966 Dinman 307-2l1X 3,253,158 5/1966 Horgan 307-223 X tiolle. A log1c gate shift circuit comprising, lIl combma 3,456,126 7/1969 Kaplan n logic gate means, when n is an integer greater than JOHN HEYM AN Primary Examiner two; means for applying an output of each F gate means M1LLER,ASS1StantEXam1ne1' back to the same gate means, where j refers to each of the gate means;

means for applying an output of each 1 gate means 307211, 221, 223; 328-43, 92

to the -{-1 gate means, when a j-f-l gate is present;

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent NO- Dated October 6: Inventor(s) R. O. Winder It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 5 llne 60 "x should be --x "z." should be --x.- J J Column 7 line 23 "2, 2, 1, 1" should be Column 8 line 25 Cancel the entire line lines 25-30 Should read --gate, where refers to each gate and 9-- Column 9 line 3 "x. should be --?c.

Signed and sealed this 27th day of April 1 971 (SEAL) Attest:

EDWARD M.FLETCHER,JR. WILLIAM E. SCHUYLER, JR. Attesting Officer Commissioner of Patents FORM PO-OSU (10-65) uscoMM-Dc 50375-p59 uS. GOVERNMKT PINTING DFFICEi l. 0-!6-834 

